9780201618600

This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx.Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design.For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.

Preface

iii

Introduction

1

(6)

References

5

(2)

Basic Language Constructs

7

(10)

Preliminaries

7

(2)

Identifiers

7

(1)

Operators

8

(1)

Values

8

(1)

Expressions

9

(1)

Datatypes

9

(3)

Nets

9

(1)

Registers

9

(1)

Integer

9

(1)

Real

10

(1)

Time

10

(1)

Events

10

(1)

Bitvector

10

(1)

Concatenation and Replication

11

(1)

Arrays

11

(1)

Parameters

11

(1)

Preprocessor Directives

12

(1)

Modules

12

(3)

Port connection rules

14

(1)

Port Lists

14

(1)

Hierarchical Names

15

(1)

Conclusion

15

(2)

Exercises

16

(1)

References

16

(1)

Structural and Behavioral Specification

17

(20)

Introduction

17

(1)

Basic Gates

18

(4)

Structural Modules Using Basic Gates

19

(1)

User Defined Primitives

20

(2)

Modeling Levels

22

(1)

Writing Styles

23

(1)

Synthesizable Operations

24

(2)

Continuous Assignments

26

(11)

Operator Inference: Ripple versus Carry Look-ahead

27

(3)

Example: Arithmetic and Logic Unit

30

(3)

Exercises

33

(3)

References

36

(1)

Simulation

37

(8)

Types of Simulators

37

(2)

Using the VCS Simulator

39

(1)

Testbenches

39

(4)

Debugging

43

(2)

Exercises

43

(2)

Procedural Specification

45

(28)

The always block

45

(2)

Blocks

46

(1)

Always Blocks with Multicycle Execution Time

46

(1)

Functions and Tasks

47

(2)

Blocking and Non-blocking Assignments

49

(1)

Control Constructs

50

(2)

IF statements

50

(1)

Looping Statements

50

(1)

Examples

51

(1)

Synthesis of Conditional Constructs

52

(4)

Case Statements

53

(3)

Example: Combinational Modules

56

(1)

Flipflops versus Latches

57

(7)

Examples Using Flipflops

60

(4)

Memory

64

(3)

Conclusion

67

(6)

Exercises

67

(4)

References

71

(2)

Design Approaches for Single Modules

73

(28)

Introduction

73

(1)

Basic Design Methodology

73

(2)

The Specification

75

(1)

Structuring the Design

75

(3)

Design Example 1---A Simple Down Counter

78

(4)

Specification

78

(1)

Determine the Control Strategy

79

(1)

Determine the RTL Structure of the Design

79

(1)

Capture the Design As Verilog

80

(1)

Verify Correctness of the Design

81

(1)

Example 2---Unsigned Parallel-Serial Multiplier

82

(6)

Determine the Control Strategy

84

(1)

Determine the RTL Structure of the Design

84

(2)

Capture the Design As Verilog

86

(2)

An Alternative Approach to Specifying Flipflops

88

(1)

Common Problems and Fixes

89

(5)

Accidental Instantiation of Latches

89

(1)

Incomplete Timing Specifications (Sensitivity Lists)

90

(1)

Unintentional Specification of Wired-Or Logic

91

(1)

Improper Use of Loop Constructs

92

(2)

Debugging Strategies

94

(1)

Conclusion

94

(7)

Exercises

95

(6)

Validation of Single Modules

101

(10)

Introduction

101

(1)

Sources of Verification Vectors

101

(1)

Verification Testbench Coding Approaches

102

(2)

Absolute versus Relative Timing

102

(1)

Reading in Verification Vector Files

103

(1)

Post-Synthesis Verification

104

(1)

Formal Verification

105

(3)

Equivalence Checkers

105

(1)

Model Checkers

106

(2)

System-level Verification

108

(1)

Conclusion

108

(3)

Exercises

108

(3)

Finite State Machine Styles

111

(16)

Introduction

111

(1)

Synthesis of State Machines

111

(5)

Classical Model

111

(1)

Explicit Specification Style

111

(3)

Implicit Specification Style

114

(2)

Example Specifications

116

(11)

Booth multiplier

116

(3)

First-in first-out buffer (FIFO)

119

(6)

Exercises

125

(1)

References

126

(1)

Control-Point Writing Style

127

(10)

Introduction

127

(1)

Instantiation of Parameterized Modules

128

(1)

Control-Point Style

128

(3)

Using Vendor's Components

131

(2)

Booth Multiplier

133

(1)

Conclusion

133

(4)

Exercises

134

(2)

References

136

(1)

Managing Complexity---Large Designs

137

(40)

Steps in High-Level Design

137

(4)

Design Partitioning

141

(2)

Controller Design Styles

143

(1)

Examples of Explicit Style---Motion Estimator

143

(7)

Datapath Design

147

(3)

Example of Implicit Style---Cache Store

150

(9)

Another Implicit Style Example: MIPS200

159

(14)

Testing the MIPS200

170

(1)

Notes on the MIPS200 Testbench

171

(1)

RTL and Control-Point Specifications of MIPS

172

(1)

Conclusion

173

(4)

Exercises

173

(3)

References

176

(1)

Improving Timing, Area, and Power

177

(20)

Introduction

177

(1)

Timing Issues in Design

177

(11)

Delay Calculations

179

(1)

Timing Design with Edge-Triggered Flipflops

180

(3)

Timing Design with Latches

183

(1)

Timing-Aware Design

184

(4)

Low Power Design

188

(4)

Power Consumption in CMOS Circuits

188

(1)

Design for Low Power

189

(3)

CAD Tools in Low-Power Design

192

(1)

Area Issues in Design

192

(2)

Conclusion

194

(3)

Exercises

194

(2)

References

196

(1)

Design Compilation

197

(20)

Introduction

197

(2)

Running Example: Alarm Clock

199

(1)

Setting Up

200

(5)

Notes on the Setup File

203

(2)

Invoking Synthesis

205

(3)

Notes on the Aclock Script File

205

(3)

The Log File

208

(9)

Exercises

215

(1)

References

215

(2)

Synthesis to Standard Cells

217

(12)

Introduction

217

(5)

Synthesis Flow

222

(5)

Conclusion

227

(2)

Exercises

227

(1)

References

228

(1)

Synthesis to FPGA

229

(20)

FPGA As a Target Technology

229

(2)

Using the Altera Tools

231

(1)

Using the Xilinx Tools

232

(3)

Generating Memory Arrays

235

(3)

Using Look-up Tables (LUTs) As Memory (such as Xilinx)

236

(1)

Using Embedded Array Blocks As Memory (such as Altera)

236

(2)

Using Embedded Arrays As ROM

238

(2)

FPGA Reports

240

(3)

Gate-Level Simulation

243

(3)

Some Usual Suspects

245

(1)

Downloading the Implemented Design

245

(1)

Conclusion

246

(3)

Exercises

247

(1)

References

247

(2)

Gate-Level Simulation and Testing

249

(12)

Ad-hoc Test Techniques

249

(1)

Scan Insertion in Synthesis

250

(1)

Built-in Selt Test

251

(10)

Specialized Tests: An Example

252

(6)

Exercises

258

(1)

References

258

(3)

Alternative Writing Styles

261

(24)

Introduction

261

(1)

Behavioral Compiler Styles

261

(9)

Booth Multiplier

267

(1)

Behavioral Compiler---A Summary

268

(2)

Self-Timed Style

270

(8)

Encapsulated Style

278

(4)

Future HDL Development

282

(3)

Exercises

282

(1)

References

283

(2)

Mixed Technology Design

285

(14)

Introduction

285

(1)

Digital/Analog

285

(5)

Hardware/Software

290

(4)

Simulation of Large Hardware Designs

290

(1)

Hardware Software Co-Design

290

(2)

Embedded Core Design

292

(1)

Design Languages for SOC (system-on-a-chip)

293

(1)

A Small Example

294

(5)

References

296

(3)

Appendix A Verilog Examples

299

(12)

A.1 Combinational Logic Structures

299

(8)

A.2 Sequential Logic Structures

307

(4)

Appendix B http://www.prenhall.com/smith/franzon

Index

311

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Preface In the last few years, the way that digital hardware is designed has undergone a reinvention. On one hand, manual design with schematic entry tools has been replaced by synthesis from high level specifications. On the other hand, custom integrated circuits are being supplanted by field programmable gate arrays (FPGA) for many applications. This text seeks to help students take their place in this new environment by making it more accessible. Currently hardware synthesis is complex and not at all like the software compilation to which it is superficially analogous. It might take a competent hardware designer a year or more to become fluent in this technology. The subsets of the two broad-based hardware description languages in current use, Verilog and VHDL, permit myriad different specifications of even the simplest module, with structural and behavioral constructs intermixed at will. Each different description may give a different result and presents different synthesis problems. What is needed is another standardization and simplification like that of Mead and Conway, which availed an earlier VLSI technology to a wider group of users. This book tries to do this by selecting the simpler language, Verilog, and standardizing the methodology to the point where seniors and first-year graduates can see medium to complex designs through to gate-level simulation in a single semester. The text is neither a complete description of the Verilog language, nor simulation, nor synthesizers, nor FPGA chip fitting tools. For these, the reader should consult the large numbers of corresponding manuals. However, using this text, together with the example tools, students can and do get interesting projects working in a single semester course. This could be a semester well spent since the demand from industry for people with this knowledge seems to exceed even that for systems software expertise. After this, with the confidence of having navigated a complete pass through the process, readers can graduate to more esoteric designs and consult the many available manuals at their leisure. There are several other good books in this general area. Of recent ones, we mention a few: First Smith97 (no relation) is an outstanding encyclopedic reference on all matters to do with ASICS. Here the emphasis is on schematic design, layout, and device physics supplemented by specifications in VHDL or Verilog. Then there are books such as Palnitkar96, Arnold99, and Ciletti99 concentrating specifically on the Verilog language itself. In all of the above, the pedagogical approach has really been to go first through all the language constructs in Verilog available to simulation, and then present the limitations of synthesis afterwards. This is to be contrasted with our treatment in which synthesis issues are introduced from the outset, incorporated into the material throughout, and designed to get students working with synthesis early. Next there are some works aimed at an audience already familiar with high-level design methodology and more oriented to specialized reference. Karup97 is really a compendium of tips and case studies in VHDL/Verilog and Synopsys with the corresponding solutions; Keating98 contains tool usage and style recommendations, specifically for modules intended for reuse in the intellectual property market, but without working examples. So these are more suitable as supplements to some other basic text. We should also mention the series of books on synthesis by Gajski and Micheli. These are a different kind of book, more oriented to research in the area, and to the few who will design the synthesizers, rather than to the many who will use them to create practical designs and get a job. Yet there is still no book that covers style recommendations specifically oriented to synthesis, that is illustrated with practical working examples, and that is accessible to the reader who wants to get a start in this field. This is a void that needs to be filled and we are hopeful that this book may do so. All the worked examples and the problems at the end of each chapter have been synthesized and successfully verified by simulation at gate level. The material has been tested in classes over three years aimed at seniors and first-year graduate students having a prerequisite of an introductory course in computer organization and a working knowledge of Unix and X windows. At the moment most industrial designers still prefer this environment, although the tools are now becoming available in the NT and Linux environments. Synthesis and fitting tools are usually available to universities at nominal maintenance fees under vendors'' "university programs." Sometimes a simulator is packaged with a tool suite, sometimes not. In what follows, the exercises have been worked out using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Of course this is somewhat specific and the reader''s location may be committed to alternative tools. We would have really liked to have compared synthesizers available from other vendors. There is really no good solution to this, since even at university pricing, any one site (including ours) cannot afford all the alternatives, nor commit the time and resources involved. All we can do is try to choose some of the best tools currently available and trust that many of the issues faced by users in other environments will be similar. For example even though Verilog and VHDL are rather different, the subsets used for synthesis by the major vendors are quite similar at the moment, which is why automatic translators are available. A complete list of vendors offering tools in the separate areas relevant to this book, such as simulation, synthesis, and FPGA, are listed at regular intervals in trade magazines including Integrated System Design(www.isdmag.com). Here the interested reader can gain ready access to the vendor representatives or Web pages to discover the relative advantages of the tools and what is available in the various university programs. The material of this book is suitable for seniors or first-year graduate students who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary for the exercises. Some knowledge of a programming language such as ''C'' or Java is desirable but not necessary. We usually find that students from a computer science background come to the course with more intuition of the software while students from an electrical engineering background bring more of a intuition on gate networks. So the two arrive at the course with about the same potential to start in on this material. We should give some explanation of the ordering of the chapters, which might seem a little peculiar at first. This is one of those subjects in which students learn by doing. Accordingly, our approach has been to introduce the use of the simulator and then the synthesizers at the earliest practical point. In this way the students should be able to ramp up on the tool learning curve and follow a trial run of a small design all the way through high-level simulation, the design compiler, FPGA, fitting, and gate-level simulation by about the middle of the semester. With this under their belts, they will be better psychologically prepared to move onto a larger independent project, the behavioral compiler, or download to and test real hardware in the time remaining to them. Thus the ordering we have chosen may be at the cost of breaking the continuity of the treatment of the design language and the examples of specification. If the user of this book disagrees with this philosophy, there is al4ays the option of reordering the chapters accordingly, say by delaying the introduction of simulation of Chapter 4 until the Chapter 7 o

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Verilog Styles for Synthesis of Digital Systems

Verilog Styles for Synthesis of Digital Systems

0201618605

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