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9780201618600

Verilog Styles for Synthesis of Digital Systems

  • ISBN 13:

    9780201618600

  • ISBN 10:

    0201618605

  • Edition: 1st
  • Format: Paperback
  • Copyright: 11/21/2019
  • Publisher: Pearson

Note: Not guaranteed to come with supplemental materials (access cards, study guides, lab manuals, CDs, etc.)

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Summary

This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx.Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design.For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.

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