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| The Fabrics | |
| Introduction | |
| A Historical Perspective | |
| Issues in Digital Integrated Circuit Design | |
| Quality Metrics of a Digital Design | |
| The Manufacturing Process | |
| The CMOS Manufacturing Process | |
| Design Rules-The Contract between Designer and Process Engineer | |
| Packaging Integrated Circuits | |
| Perspective-Trends i... MORE | |
| The Devices | |
| The Diode | |
| The MOS(FET) Transistor | |
| A Word on Process Variations | |
| Perspective: Technology Scaling | |
| The Wire | |
| A First Glance | |
| Interconnect Parameters-Capitance, Resistance, and Inductance | |
| Electrical Wire Models | |
| SPICE Wire Models | |
| Perspective: A Look into the Future | |
| A Circuit Perspective | |
| The CMOS Inverter | |
| The Static CMOS Inverter-An Intuitive Perspective | |
| Evaluating the Robustness of the CMOS Inverter: The Static Behavior | |
| Performance of CMOS Inverter: The Dynamic Behavior | |
| Power, Energy, and Energy-Delay | |
| Perspective: Technology Scaling and Its Impact on the Inverter Metrics | |
| Designing Combinational Logic Gates in CMOS | |
| Static CMOS Design | |
| Dynamic CMOS Design | |
| How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era | |
| Designing Sequential Logic Circuits | |
| Timing Metrics for Sequential Circuits | |
| Classification of Memory Elements | |
| Static Latches and Registers | |
| Dynamic Latches and Registers | |
| Pulse Registers | |
| Sense-Amplifier Based Registers | |
| Pipelining: An Approach to Optimize Sequential Circuits | |
| Non-Bistable Sequential Circuits | |
| Perspective: Choosing a Clocking Strategy | |
| A System Perspective | |
| Implementation Strategies for Digital ICS | |
| From Custom to Semicustom and Structured-Array Design Approaches | |
| Custom Circuit Design | |
| Cell-Based Design Methodology | |
| Array-Based Implementation Approaches | |
| Perspective-The Implementation Platform of the Future | |
| Coping with Interconnect | |
| Capacitive Parasitics | |
| Resistive Parasitics | |
| Inductive Parasitics | |
| Advanced Interconnect Techniques | |
| Perspective: Networks-on-a-Chip | |
| Timing Issues in Digital Circuits | |
| Timing Classification of Digital Systems | |
| Synchronous Design-An In-Depth Perspective | |
| Self-Timed Circuit Design | |
| Synchronizers and Arbiters | |
| Clock Synthesis and Synchronization Using a Phased-Locked Loop | |
| Future Directions and Perspectives | |
| Designing Arithmetic Building Blocks | |
| Datapaths in Digital Processor Architectures | |
| The Adder | |
| The Multiplier | |
| The Shifter | |
| Other Arithmetic Operators | |
| Power and Spped Trade-Offs in Datapath Structures | |
| Perspective: Design as a Trade-off | |
| Designing Memory and Array Structures | |
| The Memory Core | |
| Memory Peripheral Circuitry | |
| Memory Reliability and Yield | |
| Power Dissipation in Memories | |
| Case Studies in Memory Design | |
| Perspective: Semiconductor Memory Trends and Evolutions | |
| Problem Solutions | |
| Index | |
| Table of Contents provided by Publisher. All Rights Reserved. |