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| Web Site for the Book | p. iv |
| About the Author | p. xi |
| Preface | p. xiii |
| Reader's Guide | p. 1 |
| Outline of the Book | p. 2 |
| A Roadmap for Readers and Instructors | p. 2 |
| Why Study Computer Organization and Architecture | p. 3 |
| Internet and Web Resources | p. 4 |
| Overview | p. 7 |
| Introduction | p. 8 |
| Organization... MORE | p. 9 |
| Structure and Function | p. 10 |
| Key Terms and Review Questions | p. 15 |
| Computer Evolution and Performance | p. 16 |
| A Brief History of Computers | p. 17 |
| Designing for Performance | p. 38 |
| The Evolution of the Intel x86 Architecture | p. 44 |
| Embedded Systems and the ARM | p. 46 |
| Performance Assessment | p. 50 |
| Recommended Reading and Web Sites | p. 57 |
| Key Terms, Review Questions, and Problems | p. 59 |
| The Computer System | p. 63 |
| A Top-Level View of Computer Function and Interconnection | p. 65 |
| Computer Components | p. 66 |
| Computer Function | p. 68 |
| Interconnection Structures | p. 83 |
| Bus Interconnection | p. 85 |
| PCI | p. 95 |
| Recommended Reading and Web Sites | p. 104 |
| Key Terms, Review Questions, and Problems | p. 104 |
| Appendix 3A Timing Diagrams | p. 108 |
| Cache Memory | p. 110 |
| Computer Memory System Overview | p. 111 |
| Cache Memory Principles | p. 118 |
| Elements of Cache Design | p. 121 |
| Pentium 4 Cache Organization | p. 140 |
| ARM Cache Organization | p. 143 |
| Recommended Reading | p. 145 |
| Key Terms, Review Questions, and Problems | p. 146 |
| Appendix 4A Performance Characteristics of Two-Level Memories | p. 151 |
| Internal Memory Technology | p. 158 |
| Semiconductor Main Memory | p. 159 |
| Error Correction | p. 169 |
| Advanced DRAM Organization | p. 173 |
| Recommended Reading and Web Sites | p. 179 |
| Key Terms, Review Questions, and Problems | p. 180 |
| External Memory | p. 184 |
| Magnetic Disk | p. 185 |
| RAID | p. 194 |
| Optical Memory | p. 203 |
| Magnetic Tape | p. 210 |
| Recommended Reading and Web Sites | p. 212 |
| Key Terms, Review Questions, and Problems | p. 214 |
| Input/Output | p. 217 |
| External Devices | p. 219 |
| I/O Modules | p. 222 |
| Programmed I/O | p. 224 |
| Interrupt-Driven I/O | p. 228 |
| Direct Memory Access | p. 236 |
| I/O Channels and Processors | p. 242 |
| The External Interface: Fire Wire and Infiniband | p. 244 |
| Recommended Reading and Web Sites | p. 253 |
| Key Terms, Review Questions, and Problems | p. 254 |
| Operating System Support | p. 259 |
| Operating System Overview | p. 260 |
| Scheduling | p. 271 |
| Memory Management | p. 277 |
| Pentium Memory Management | p. 288 |
| ARM Memory Management | p. 293 |
| Recommended Reading and Web Sites | p. 298 |
| Key Terms, Review Questions, and Problems | p. 299 |
| The Central Processing Unit | p. 303 |
| Computer Arithmetic | p. 305 |
| The Arithmetic and Logic Unit (ALU) | p. 306 |
| Integer Representation | p. 307 |
| Integer Arithmetic | p. 312 |
| Floating-Point Representation | p. 327 |
| Floating-Point Arithmetic | p. 334 |
| Recommended Reading and Web Sites | p. 342 |
| Key Terms, Review Questions, and Problems | p. 344 |
| Instruction Sets: Characteristics and Functions | p. 348 |
| Machine Instruction Characteristics and Functions | p. 348 |
| Types of Operands | p. 356 |
| Intel x86 and ARM Data Types | p. 358 |
| Types of Operations | p. 362 |
| Intel x86 and ARM Operation Types | p. 374 |
| Recommended Reading | p. 384 |
| Key Terms, Review Questions, and Problems | p. 385 |
| Appendix 10A Stacks | p. 390 |
| Appendix 10B Little, Big, and Bi-Endian | p. 396 |
| Instruction Sets: Addressing Modes and Formats | p. 400 |
| Addressing | p. 401 |
| x86 and ARM Addressing Modes | p. 408 |
| Instruction Formats | p. 413 |
| x86 and ARM Instruction Formats | p. 421 |
| Assembly Language | p. 426 |
| Recommended Reading | p. 428 |
| Key Terms, Review Questions, and Problems | p. 428 |
| Processor Structure and Function | p. 432 |
| Processor Organization | p. 433 |
| Register Organization | p. 435 |
| The Instruction Cycle | p. 440 |
| Instruction Pipelining | p. 444 |
| The x86 Processor Family | p. 461 |
| The ARM Processor | p. 469 |
| Recommended Reading | p. 475 |
| Key Terms, Review Questions, and Problems | p. 476 |
| Reduced Instruction Set Computers (RISCs) | p. 480 |
| Instruction Execution Characteristics | p. 482 |
| The Use of a Large Register File | p. 487 |
| Compiler-Based Register Optimization | p. 492 |
| Reduced Instruction Set Architecture | p. 494 |
| RISC Pipelining | p. 500 |
| MIPS R4000 | p. 504 |
| SPARC | p. 511 |
| The RISC versus CISC Controversy | p. 517 |
| Recommended Reading | p. 518 |
| Key Terms, Review Questions, and Problems | p. 518 |
| Instruction-Level Parallelism and Superscalar Processors | p. 522 |
| Overview | p. 524 |
| Design Issues | p. 528 |
| Pentium 4 | p. 538 |
| ARM Cortex-A8 | p. 544 |
| Recommended Reading | p. 552 |
| Key Terms, Review Questions, and Problems | p. 554 |
| The Control Unit | p. 559 |
| Control Unit Operation | p. 561 |
| Micro-operations | p. 563 |
| Control of the Processor | p. 569 |
| Hardwired Implementation | p. 581 |
| Recommended Reading | p. 584 |
| Key Terms, Review Questions, and Problems | p. 584 |
| Microprogrammed Control | p. 586 |
| Basic Concepts | p. 587 |
| Microinstruction Sequencing | p. 596 |
| Microinstruction Execution | p. 602 |
| TI 8800 | p. 614 |
| Recommended Reading | p. 624 |
| Key Terms, Review Questions, and Problems | p. 625 |
| Parallel Organization | p. 627 |
| Parallel Processing | p. 628 |
| The Use of Multiple Processors | p. 630 |
| Symmetric Multiprocessors | p. 632 |
| Cache Coherence and the MESI Protocol | p. 640 |
| Multithreading and Chip Multiprocessors | p. 646 |
| Clusters | p. 653 |
| Nonuniform Memory Access Computers | p. 660 |
| Vector Computation | p. 664 |
| Recommended Reading and Web Sites | p. 676 |
| Key Terms, Review Questions, and Problems | p. 677 |
| Multicore Computers | p. 684 |
| Hardware Performance Issues | p. 685 |
| Software Performance Issues | p. 690 |
| Multicore Organization | p. 694 |
| Intel x86 Multicore Organization | p. 696 |
| ARM11 MPCore | p. 699 |
| Recommended Reading and Web Sites | p. 704 |
| Key Terms, Review Questions, and Problems | p. 705 |
| Projects for Teaching Computer Organization and Architecture | p. 707 |
| Interactive Simulations | p. 708 |
| Research Projects | p. 708 |
| Simulation Projects | p. 710 |
| Assembly Language Projects | p. 711 |
| Reading/Report Assignments | p. 711 |
| Writing Assignments | p. 712 |
| Test Bank | p. 712 |
| Assembly Language and Related Topics | p. 713 |
| Assembly Language | p. 714 |
| Assemblers | p. 723 |
| Loading and Linking | p. 728 |
| Recommended Reading and Web Sites | p. 735 |
| Key Terms, Review Questions, and Problems | p. 736 |
| Online Chapters WilliamStalling.com/COA/COA8e.html | |
| Number Systems 19-1 | |
| The Decimal System 19-2 | |
| The Binary System 19-2 | |
| Converting between Binary and Decimal 19-3 | |
| Hexadecimal Notation 19-5 | |
| Key Terms, Review Questions, and Problems 19-8 | |
| Digital Logic 20-1 | |
| Boolean Algebra 20-2 | |
| Gates 20-4 | |
| Combinational Circuits 20-7 | |
| Sequential Circuits 20-24 | |
| Programmable Logic Devices 20-33 | |
| Recommended Reading and Web Site 20-38 | |
| Key Terms and Problems 20-39 | |
| The IA-64 Architecture 21-1 | |
| Motivation 21-3 | |
| General Organization 21-4 | |
| Predication, Speculation, and Software Pipelining 21-6 | |
| IA-64 Instruction Set Architecture 21-23 | |
| Itanium Organization 21-28 | |
| Recommended Reading and Web Sites 21-31 | |
| Key Terms, Review Questions, and Problems 21-32 | |
| Online Appendices William Stallings.com/COA/COA8e.html | |
| Hash Tables | |
| Victim Cache Strategies | |
| Victim Cache | |
| Selective Victim Cache | |
| Interleaved Memory | |
| International Reference Alphabet | |
| Virtual Memory Page Replacement Algorithms | |
| Recursive Procedures | |
| Recursion | |
| Activation Tree Representation | |
| Stack Processing | |
| Recursion and Iteration | |
| Additional Instruction Pipeline Topics | |
| Pipeline Reservation Tables | |
| Reorder Buffers | |
| Scoreboarding | |
| Tomasulo's Algorithm | |
| Linear Tape Open Technology | |
| DDR SDRAM | |
| Glossary | p. 740 |
| References | p. 750 |
| Index | p. 763 |
| Table of Contents provided by Ingram. All Rights Reserved. |