Digital System Design with VHDL is intended both for students on Digital Design courses and practitioners who would like to integrate digital design and VHDL synthesis in the workplace.

Its unique approach combines the principles of digital design with a guide to the use of VHDL. Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance.

Features:

• a practical perspective is obtained by the inclusion of real-life examples
• an emphasis on software engineering practices encourages clear coding and adequate documentation of the process
• demonstrates the effects of particular coding styles on synthesis and simulation efficiency
• covers the major VHDL standards
• includes an appendix with examples in Verilog