Rent 9780470052624 | Verilog for Digital Design | Frank Vahid (Dept. of Computer Science & Engineering, University of California - Riverside); Roman Lysecky (Dept. of Electrical and Computer Engineering, University of Arizona) @knetbooks.com

Summary Table of Contents

* Ideal as either a standalone introductory guide or in tandem with Vahid's Digital Design to allow for greater language coverage, this is an accessible introductory guide to hardware description language * Verilog is a hardware description language used to model electronic systems (sometimes called Verilog HDL) and this book is helpful for anyone who is starting out and learning the language * Focuses on application and use of the language, rather than just teaching the basics of the language

Verilog for Digital D... MORE

Preface	p. vii
To Those About to Study Verilog	p. vii
To Teachers of Verilog	p. vii
About the Book	p. ix
Chapter Overview	p. ix
Accompanying Resources	p. ix
Formatting	p. x
Acknowledgments	p. x
About the Authors	p. x
Contents	p. xiii
Introduction	p. 1
Digital ... MORESystems	p. 1
Hardware Description Languages	p. 2
HDLs for Design and Synthesis	p. 6
Combinational Logic Design	p. 9
AND, OR, and NOT Gates	p. 9
Modules and Ports	p. 9
Module Procedures-always	p. 11
Simulation and Testbenches-A First Look	p. 13
Variables and nets	p. 15
Module procedures-initial	p. 15
Delay control	p. 16
Comments	p. 17
Combinational Circuit Structure	p. 18
Module Instantiations	p. 18
Port Connections	p. 20
Simulating The Circuit	p. 21
Top-Down Design-Combinational Behavior to Structure	p. 23
Procedures with If-Else Statements	p. 25
Multiple Module Descriptions for One Module	p. 28
Common Pitfalls	p. 29
Missing inputs from event control expression	p. 29
Outputs not assigned on every pass	p. 30
Hierarchical Circuits	p. 32
Using Modules as Instances	p. 32
Built-In Logic Gates	p. 34
Sequential Logic Design	p. 35
Register Behavior	p. 35
Vectors	p. 35
Constant Numbers	p. 37
Synchronous Storage Using a reg Variable	p. 37
Testbenches with Clocks	p. 38
Common Pitfalls	p. 40
Using an always procedure instead of an initial procedure	p. 40
Not including any delay control or event control in an always procedure	p. 40
Not initializing all input ports	p. 41
Not declaring an identifier used in a port connection	p. 42
Finite-State Machines (FSMs)-Sequential Behavior	p. 43
Multiple Always Procedures and Shared Variables	p. 43
Parameters (Constants)	p. 44
Procedures with Case Statements	p. 44
Self-Checking Testbenches	p. 46
Top-Down Design-FSMs to Controller Structure	p. 49
Common Pitfall	p. 51
Not assigning outputs in every state	p. 51
More Simulation Concepts	p. 53
The Simulation Cycle	p. 53
Scheduled Events	p. 56
Resets	p. 59
Describing Safe FSMs	p. 62
Datapath Components	p. 65
Multifunction Registers	p. 65
Continuous Assignment Statement	p. 66
Common Pitfall	p. 68
Not using a begin-end block with every if statement	p. 68
Adders	p. 69
Built-In Arithmetic Operations	p. 69
Concatenation	p. 72
Blocking Versus Non-Blocking Assignments	p. 72
Left-Side Concatenation	p. 73
Shift Registers	p. 74
Procedures with For Loop Statements	p. 76
Integer Variables	p. 77
Relational, Logical, and Equality Operators	p. 78
File Input and Output	p. 79
Functions and tasks	p. 80
File input and output procedures	p. 81
While loops	p. 82
Common Pitfall	p. 83
Creating a loop that cannot be unrolled during synthesis	p. 83
Comparators	p. 85
Unsigned and Signed Numbers	p. 85
Common Pitfall	p. 87
Unintentional use of one of Verilog's many automatic conversions	p. 87
Register Files	p. 88
Using High-Impedance Values	p. 90
Conditional Operator "?"	p. 91
Multiple Drivers of One Net	p. 93
Arrays	p. 95
Common Pitfall	p. 96
Confusing bitwise and logical operators	p. 96
Register-Transfer Level (RTL) Design	p. 97
High-Level State Machine (HLSM) Behavior	p. 97
Top-Down Design-HLSM to Controller and Datapath	p. 102
Describing a State Machine using One Procedure	p. 109
Improving Timing Realism	p. 112
Delay Control on Right Side of Assignment Statements	p. 112
Algorithmic-Level Behavior	p. 114
Top-Down Design-Converting Algorithmic-Level Behavior to RTL	p. 119
Automated Synthesis from the Algorithmic-Level	p. 122
Simulation Speed	p. 122
Memory	p. 123
Verilog Mini-Reference	p. 129
Basic Syntax	p. 129
Comments	p. 129
Identifiers	p. 130
Keywords	p. 130
Numbers	p. 131
Integer Constant	p. 131
Real Constant	p. 133
Strings	p. 133
Declarations	p. 134
Net (Wire)	p. 134
Module	p. 134
Ports	p. 134
Parameter	p. 135
Local Parameter	p. 136
Variable (Reg)	p. 137
Statements	p. 137
Assignment Statement	p. 137
Blocking Assignment	p. 137
Non-blocking Assignment	p. 138
Continuous Assignment	p. 138
Case Statement	p. 139
If-Else Statement	p. 141
Loop Statement	p. 142
For Loop	p. 142
Repeat Loop	p. 143
While Loop	p. 143
Null	p. 144
Procedure	p. 144
Always Procedure	p. 144
Initial Procedure	p. 146
Module Instantiation	p. 146
Port Connection	p. 147
Parameter Assignment	p. 147
Timing control	p. 148
Delay Control	p. 148
Event Control	p. 149
Timescale Directive	p. 149
Wait Statement	p. 150
Operators	p. 150
Arithmetic	p. 150
Bitwise	p. 151
Concatenation	p. 151
Conditional	p. 152
Equality	p. 152
Logical	p. 153
Reduction	p. 153
Relational	p. 154
Shift	p. 154
Operator Precedence	p. 155
System Tasks and Functions	p. 155
$display and $write	p. 156
File Input and Output	p. 157
$fopen	p. 157
$feof	p. 157
$fgetc	p. 158
$fclose	p. 158
$fdisplay and $fwrite	p. 158
$readmemb and $readmemh	p. 158
$signed and $unsigned	p. 159
$time	p. 159
Common Data Types	p. 159
Array	p. 159
Integer	p. 160
Signed	p. 160
Vector	p. 160
Index	p. 163
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