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Structured Computer Organization

ISBN: 9780131485211 | 0131485210
Edition: 5th
Format: Hardcover
Publisher: Prentice Hall
Pub. Date: 1/1/2006

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SummaryTable of ContentsAuthor Biography
This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture.Tanenbaumrs"s renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the authorrs"s popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. A CD-ROM for assembly language programmers is available for teachers.For all computer professionals and engineers who need an overview or introduction to computer architecture.
Prefacexviii
Introduction
1(50)
Structured Computer Organization
2(11)
... MORELanguages, Levels, and Virtual Machines
2(3)
Contemporary Multilevel Machines
5(3)
Evolution of Multilevel Machines
8(5)
Milestones in Computer Architecture
13(14)
The Zeroth Generation---Mechanical Computers (1642-1945)
14(2)
The First Generation---Vacuum Tubes (1945-1955)
16(3)
The Second Generation---Transistors (1955-1965)
19(3)
The Third Generation---Integrated Circuits (1965-1980)
22(1)
The Fourth Generation---Very Large Scale Integration (1980-?)
23(3)
The Fifth Generation---Invisible Computers
26(1)
The Computer Zoo
27(10)
Technological and Economic Forces
27(2)
The Computer Spectrum
29(1)
Disposable Computers
29(2)
Microcontrollers
31(2)
Game Computers
33(1)
Personal Computers
34(1)
Servers
34(1)
Collections of Workstations
34(2)
Mainframes
36(1)
Example Computer Families
37(9)
Introduction to the Pentium 4
37(5)
Introduction to the UltraSPARC III
42(2)
Introduction to the 8051
44(2)
Metric Units
46(1)
Outline of This Book
47(4)
Computer Systems Organization
51(84)
Processors
51(18)
CPU Organization
52(2)
Instruction Execution
54(4)
RISC versus CISC
58(1)
Design Principles for Modern Computers
59(2)
Instruction-Level Parallelism
61(4)
Processor-Level Parallelism
65(4)
Primary Memory
69(12)
Bits
69(1)
Memory Addresses
70(1)
Byte Ordering
71(2)
Error-Correcting Codes
73(4)
Cache Memory
77(3)
Memory Packaging and Types
80(1)
Secondary Memory
81(21)
Memory Hierarchies
81(1)
Magnetic Disks
82(4)
Floppy Disks
86(1)
IDE Disks
86(2)
SCSI Disks
88(1)
Raid
89(4)
CD-ROMs
93(4)
CD-Recordables
97(2)
CD-Rewritables
99(1)
DVD
99(3)
Blu-Ray
102(1)
Input/Output
102(29)
Buses
102(3)
Terminals
105(5)
Mice
110(2)
Printers
112(5)
Telecommunications Equipment
117(8)
Digital Cameras
125(2)
Character Codes
127(4)
Summary
131(4)
The Digital Logic Level
135(96)
Gates and Boolean Algebra
135(11)
Gates
136(2)
Boolean Algebra
138(2)
Implementation of Boolean Functions
140(1)
Circuit Equivalence
141(5)
Basic Digital Logic Circuits
146(13)
Integrated Circuits
146(1)
Combinational Circuits
147(5)
Arithmetic Circuits
152(5)
Clocks
157(2)
Memory
159(14)
Latches
159(2)
Flip-Flops
161(2)
Registers
163(1)
Memory Organization
164(4)
Memory Chips
168(3)
RAMs and ROMs
171(2)
CPU Chips and Buses
173(16)
CPU Chips
174(2)
Computer Buses
176(2)
Bus Width
178(2)
Bus Clocking
180(4)
Bus Arbitration
184(3)
Bus Operations
187(2)
Example CPU Chips
189(13)
The Pentium 4
189(7)
The UltraSPARC III
196(4)
The 8051
200(2)
Example Buses
202(19)
The ISA Bus
203(1)
The PCI Bus
204(8)
PCI Express
212(5)
The Universal Serial Bus
217(4)
Interfacing
221(4)
I/O Chips
221(1)
Address Decoding
222(3)
Summary
225(6)
The Microarchitecture Level
231(100)
An Example Microarchitecture
231(15)
The Data Path
232(7)
Microinstructions
239(2)
Microinstruction Control: The Mic-1
241(5)
An Example ISA: IJVM
246(9)
Stacks
246(2)
The IJVM Memory Model
248(2)
The IJVM Instruction Set
250(4)
Compiling Java to IJVM
254(1)
An Example Implementation
255(16)
Microinstructions and Notation
255(5)
Implementation of IJVM Using the Mic-1
260(11)
Design of the Microarchitecture Level
271(21)
Speed versus Cost
271(2)
Reducing the Execution Path Length
273(8)
A Design with Prefetching: The Mic-2
281(1)
A Pipelined Design: The Mic-3
281(7)
A Seven-Stage Pipeline: The Mic-4
288(4)
Improving Performance
292(19)
Cache Memory
293(6)
Branch Prediction
299(5)
Out-of-Order Execution and Register Renaming
304(5)
Speculative Execution
309(2)
Examples of the Microarchitecture Level
311(14)
The Microarchitecture of the Pentium 4 CPU
312(5)
The Microarchitecture of the UltraSPARC-III Cu CPU
317(6)
The Microarchitecture of the 8051 CPU
323(2)
Comparison of the Pentium, Ultrasparc, and 8051
325(1)
Summary
326(5)
The Instruction Set Architecture Level
331(96)
Overview of the ISA Level
333(15)
Properties of the ISA Level
333(2)
Memory Models
335(2)
Registers
337(2)
Instructions
339(1)
Overview of the Pentium 4 ISA Level
339(2)
Overview of the UltraSPARC III ISA Level
341(4)
Overview of the 8051 ISA Level
345(3)
Data Types
348(3)
Numeric Data Types
348(1)
Nonnumeric Data Types
349(1)
Data Types on the Pentium 4
350(1)
Data Types on the UltraSPARC III
350(1)
Data Types on the 8051
351(1)
Instruction Formats
351(9)
Design Criteria for Instruction Formats
352(2)
Expanding Opcodes
354(3)
The Pentium 4 Instruction Formats
357(1)
The UltraSPARC III Instruction Formats
358(1)
The 8051 Instruction Formats
359(1)
Addressing
360(15)
Addressing Modes
360(1)
Immediate Addressing
361(1)
Direct Addressing
361(1)
Register Addressing
361(1)
Register Indirect Addressing
362(1)
Indexed Addressing
363(2)
Based-Indexed Addressing
365(1)
Stack Addressing
365(4)
Addressing Modes for Branch Instructions
369(1)
Orthogonality of Opcodes and Addressing Modes
369(2)
The Pentium 4 Addressing Modes
371(2)
The UltraSPARC III Addressing Modes
373(1)
The 8051 Addressing Modes
373(1)
Discussion of Addressing Modes
374(1)
Instruction Types
375(20)
Data Movement Instructions
375(1)
Dyadic Operations
376(1)
Monadic Operations
377(2)
Comparisons and Conditional Branches
379(2)
Procedure Call Instructions
381(1)
Loop Control
382(1)
Input/Output
383(3)
The Pentium 4 Instructions
386(3)
The UltraSPARC III Instructions
389(3)
The 8051 Instructions
392(1)
Comparison of Instruction Sets
392(3)
Flow of Control
395(13)
Sequential Flow of Control and Branches
395(1)
Procedures
396(5)
Coroutines
401(3)
Traps
404(1)
Interrupts
404(4)
A Detailed Example: The Towers of Hanoi
408(3)
The Towers of Hanoi in Pentium 4 Assembly Language
409(1)
The Towers of Hanoi in UltraSPARC III Assembly Language
409(2)
The IA-64 Architecture and the it Anium 2
411(10)
The Problem with the Pentium 4
413(1)
The IA-64 Model: Explicitly Parallel Instruction Computing
414(1)
Reducing Memory References
415(1)
Instruction Scheduling
416(2)
Reducing Conditional Branches: Predication
418(2)
Speculative Loads
420(1)
Summary
421(6)
The Operating System Machine Level
427(80)
Virtual Memory
428(25)
Paging
429(2)
Implementation of Paging
431(2)
Demand Paging and the Working Set Model
433(3)
Page Replacement Policy
436(2)
Page Size and Fragmentation
438(1)
Segmentation
439(3)
Implementation of Segmentation
442(3)
Virtual Memory on the Pentium 4
445(5)
Virtual Memory on the UltraSPARC III
450(2)
Virtual Memory and Caching
452(1)
Virtual I/O Instructions
453(7)
Files
454(1)
Implementation of Virtual I/O Instructions
455(4)
Directory Management Instructions
459(1)
Virtual Instructions for Parallel Processing
460(10)
Process Creation
461(1)
Race Conditions
462(4)
Process Synchronization Using Semaphores
466(4)
Example Operating Systems
470(30)
Introduction
470(9)
Examples of Virtual Memory
479(3)
Examples of Virtual I/O
482(11)
Examples of Process Management
493(7)
Summary
500(7)
The Assembly Language Level
507(40)
Introduction to Assembly Language
508(9)
What Is an Assembly Language?
508(1)
Why Use Assembly Language?
509(3)
Format of an Assembly Language Statement
512(3)
Pseudoinstructions
515(2)
Macros
517(5)
Macro Definition, Call, and Expansion
518(2)
Macros with Parameters
520(1)
Advanced Features
521(1)
Implementation of a Macro Facility in an Assembler
521(1)
The Assembly Process
522(8)
Two-Pass Assemblers
522(1)
Pass One
523(4)
Pass Two
527(2)
The Symbol Table
529(1)
Linking and Loading
530(13)
Tasks Performed by the Linker
532(3)
Structure of an Object Module
535(1)
Binding Time and Dynamic Relocation
536(3)
Dynamic Linking
539(4)
Summary
543(4)
Parallel Computer Architectures
547(108)
On-Chip Paralellism
548(19)
Instruction-Level Parallelism
549(7)
On-Chip Multithreading
556(6)
Single-Chip Multiprocessors
562(5)
Coprocessors
567(15)
Network Processors
568(8)
Media Processors
576(5)
Cryptoprocessors
581(1)
Shared-Memory Multiprocessors
582(30)
Multiprocessors vs. Multicomputers
582(8)
Memory Semantics
590(4)
UMA Symmetric Multiprocessor Architectures
594(8)
NUMA Multiprocessors
602(9)
COMA Multiprocessors
611(1)
Message-Passing Multicomputers
612(37)
Interconnection Networks
614(3)
MPPs---Massively Parallel Processors
617(10)
Cluster Computing
627(5)
Communication Software for Multicomputers
632(3)
Scheduling
635(1)
Application-Level Shared Memory
636(7)
Performance
643(6)
Grid Computing
649(2)
Summary
651(4)
Reading List and Bibliography
655(24)
Suggestions for Further Reading
655(9)
Introduction and General Works
655(2)
Computer Systems Organization
657(1)
The Digital Logic Level
658(1)
The Microarchitecture Level
659(1)
The Instruction Set Architecture Level
659(1)
The Operating System Machine Level
660(1)
The Assembly Language Level
661(1)
Parallel Computer Architectures
661(2)
Binary and Floating-Point Numbers
663(1)
Assembly Language Programming
664(1)
Alphabetical Bibliography
664(15)
A BINARY NUMBERS
679(12)
Finite-Precision Numbers
679(2)
Radix Number Systems
681(2)
Conversion from One Radix to Another
683(2)
Negative Binary Numbers
685(3)
Binary Arithmetic
688(3)
B FLOATING-POINT NUMBERS
691(10)
Principles Of Floating Point
692(2)
IEEE Floating-Point Standard 754
694(7)
C ASSEMBLY LANGUAGE PROGRAMMING
701(56)
Overview
702(2)
Assembly Language
702(1)
A Small Assembly Language Program
703(1)
The 8088 Processor
704(5)
The Processor Cycle
705(1)
The General Registers
705(3)
Pointer Registers
708(1)
Memory and Addressing
709(6)
Memory Organization and Segments
709(2)
Addressing
711(4)
The 8088 Instruction Set
715(10)
Move, Copy and Arithmetic
715(3)
Logical, Bit and Shift Operations
718(1)
Loop and Repetitive String Operations
718(1)
Jump and Call Instructions
719(2)
Subroutine Calls
721(2)
System Calls and System Subroutines
723(2)
Final Remarks on the Instruction Set
725(1)
The Assembler
725(7)
Introduction
726(1)
The ACK-Based Tutorial Assembler as88
727(3)
Some Differences with Other 8088 Assemblers
730(2)
The Tracer
732(3)
Tracer Commands
734(1)
Getting Started
735(1)
Examples
736(21)
Hello World Example
736(4)
General Registers Example
740(2)
Call Command and Pointer Registers
742(2)
Debugging an Array Print Program
744(4)
String Manipulation and String Instructions
748(2)
Dispatch Tables
750(2)
Buffered and Random File Access
752(5)
Index757
Andrew S. Tanenbaum is a professor of computer science at the Vrije Universiteit in Amsterdam where he has taught courses in computer organization, operating systems and networks for over 30 years to thousands of students

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