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Structured Computer Organization

ISBN: 9780138546625 | 0138546622
Edition: 3rd
Format: Hardcover
Publisher: Prentice Hall Professional Technical Reference
Pub. Date: 12/1/1989

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SummaryTable of ContentsAuthor Biography
Preserving the same popular structure found in the previous four editions of this best-selling book, Andrew Tanenbaum teaches that a computer can be structured as a hierarchy of levels. In this book he covers them all, including the digital logic level, the microarchitecture level, the instruction set architecture level, the operating system machine level and the assembly language level.
PREFACExv
1 INTRODUCTION
1(30)
1.1 LANGUAGES, LEVELS, AND VIRTUAL MACHINES
3(1)
... MORE
1.2 CONTEMPORARY MULTILEVEL MACHINES
4(4)
1.3 EVOLUTION OF MULTILEVEL MACHINES
8(3)
1.4 HARDWARE, SOFTWARE, AND MULTILEVEL MACHINES
11(2)
1.5 MILESTONES IN COMPUTER ARCHITECTURE
13(14)
1.5.1 The Zeroth Generation--Mechanical Computers (1642-1945)
13(3)
1.5.2 The First Generation--Vacuum Tubes (1945-1955)
16(2)
1.5.3 The Second Generation--Transistors (1955-1965)
18(2)
1.5.4 The Third Generation--Integrated Circuits (1965-1980)
20(2)
1.5.5 The Fourth Generation--Personal Computers and VLSI (1980-199?)
22(1)
1.5.6 The Intel Family
23(2)
1.5.7 The Motorola Family
25(2)
1.6 OUTLINE OF THIS BOOK
27(4)
2 COMPUTER SYSTEMS ORGANIZATION
31(45)
2.1 PROCESSORS
31(9)
2.1.1 Instruction Execution
32(1)
2.1.2 CPU Organization
33(3)
2.1.3 Parallel Instruction Execution
36(4)
2.2 MEMORY
40(15)
2.2.1 Bits
40(1)
2.2.2 Memory Addresses
41(2)
2.2.3 Byte Ordering
43(1)
2.2.4 Error-Correcting Codes
44(4)
2.2.5 Secondary Memory
48(7)
2.3 INPUT/OUTPUT
55(17)
2.3.1 Terminals
57(5)
2.3.2 Modems
62(3)
2.3.3 Mice
65(2)
2.3.4 Printers
67(4)
2.3.5 Character Codes
71(1)
2.4 SUMMARY
72(4)
3 THE DIGITAL LOGIC LEVEL
76(85)
3.1 GATES AND BOOLEAN ALGEBRA
77(9)
3.1.1 Gates
77(2)
3.1.2 Boolean Algebra
79(1)
3.1.3 Implementation of Boolean Functions
80(2)
3.1.4 Circuit Equivalence
82(4)
3.2 BASIC DIGITAL LOGIC CIRCUITS
86(15)
3.2.1 Integrated Circuits
87(3)
3.2.2 Combinational Circuits
90(5)
3.2.3 Arithmetic Circuits
95(3)
3.2.4 Clocks
98(3)
3.3 MEMORY
101(10)
3.3.1 Latches
101(2)
3.3.2 Flip-Flops and Registers
103(2)
3.3.3 Memory Organization
105(4)
3.3.4 Memory Properties
109(2)
3.4 MICROPROCESSOR CHIPS AND BUSES
111(14)
3.4.1 Microprocessor Chips
112(2)
3.4.2 Computer Buses
114(2)
3.4.3 Synchronous Buses
116(3)
3.4.4 Asynchronous Buses
119(2)
3.4.5 Bus Arbitration
121(3)
3.4.6 Interrupt Handling
124(1)
3.5 EXAMPLE MICROPROCESSOR CHIPS
125(12)
3.5.1 The Intel 8088/80286/80386 Microprocessor Chips
126(8)
3.5.2 The Motorola 68000/68020/68030 Microprocessor Chips
134(2)
3.5.3 Comparison of the 80386 and 68030
136(1)
3.6 EXAMPLE BUSES
137(12)
3.6.1 The IBM PC Bus
137(5)
3.6.2 The IBM PC/AT Bus
142(1)
3.6.3 The VME Bus
143(6)
3.7 INTERFACING
149(6)
3.7.1 I/O Chips
151(1)
3.7.2 Address Decoding
152(3)
3.8 SUMMARY
155(6)
4 THE MICROPROGRAMMING LEVEL
161(68)
4.1 REVIEW OF THE DIGITAL LOGIC LEVEL
162(8)
4.1.1 Registers
162(1)
4.1.2 Buses
163(2)
4.1.3 Multiplexers and Decoders
165(1)
4.1.4 ALUs and Shifters
166(1)
4.1.5 Clocks
167(1)
4.1.6 Main Memory
167(2)
4.1.7 Component Packaging
169(1)
4.2 AN EXAMPLE MICROARCHITECTURE
170(8)
4.2.1 The Data Path
170(2)
4.2.2 Microinstructions
172(2)
4.2.3 Microinstruction Timing
174(3)
4.2.4 Microinstruction Sequencing
177(1)
4.3 AN EXAMPLE MACROARCHITECTURE
178(8)
4.3.1 Stacks
179(5)
4.3.2 The Macroinstruction Set
184(2)
4.4 AN EXAMPLE MICROPROGRAM
186(7)
4.4.1 The Micro Assembly Language
186(1)
4.4.2 The Example Microprogram
187(5)
4.4.3 Remarks about the Microprogram
192(1)
4.4.4 Perspective
192(1)
4.5 DESIGN OF THE MICROPROGRAMMING LEVEL
193(22)
4.5.1 Horizontal versus Vertical Microprogramming
193(6)
4.5.2 Nanoprogramming
199(3)
4.5.3 Improving Performance
202(3)
4.5.4 Pipelining
205(4)
4.5.5 Cache Memory
209(6)
4.6 EXAMPLES OF THE MICROPROGRAMMING LEVEL
215(9)
4.6.1 The Intel 8088 Microarchitecture
215(5)
4.6.2 The Motorola 68000 Microarchitecture
220(4)
4.7 SUMMARY
224(5)
5 THE CONVENTIONAL MACHINE LEVEL
229(89)
5.1 EXAMPLES OF THE CONVENTIONAL MACHINE LEVEL
229(22)
5.1.1 The Intel 8088/80286/80386 Family
230(3)
5.1.2 The Motorola 68000/68020/68030 Family
243(7)
5.1.3 Comparison of the 80386 and 68030
250(1)
5.2 INSTRUCTION FORMATS
251(10)
5.2.1 Design Criteria for Instruction Formats
251(2)
5.2.2 Expanding Opcodes
253(3)
5.2.3 Examples of Instruction Formats
256(5)
5.3 ADDRESSING
261(22)
5.3.1 Immediate Addressing
261(1)
5.3.2 Direct Addressing
262(1)
5.3.3 Register Addressing
262(1)
5.3.4 Indirect Addressing
263(2)
5.3.5 Indexing
265(1)
5.3.6 Stack Addressing
266(7)
5.3.7 Examples of Addressing
273(8)
5.3.8 Discussion of Addressing Modes
281(2)
5.4 INSTRUCTION TYPES
283(14)
5.4.1 Data Movement Instructions
283(1)
5.4.2 Dyadic Operations
284(1)
5.4.3 Monadic Operations
285(2)
5.4.4 Comparisons and Conditional Jumps
287(2)
5.4.5 Procedure Call Instructions
289(1)
5.4.6 Loop Control
290(2)
5.4.7 Input/Output
292(5)
5.5 FLOW OF CONTROL
297(15)
5.5.1 Sequential Flow of Control and Jumps
297(1)
5.5.2 Procedures
298(6)
5.5.3 Coroutines
304(3)
5.5.4 Traps
307(1)
5.5.5 Interrupts
308(4)
5.6 SUMMARY
312(6)
6 THE OPERATING SYSTEM MACHINE LEVEL
318(79)
6.1 VIRTUAL MEMORY
321(32)
6.1.1 Paging
321(3)
6.1.2 Implementation of Paging
324(3)
6.1.3 Demand Paging and the Working Set Model
327(4)
6.1.4 Page Replacement Policy
331(2)
6.1.5 Page Size and Fragmentation
333(1)
6.1.6 Segmentation
334(4)
6.1.7 Implementation of Segmentation
338(1)
6.1.8 The MULTICS Virtual Memory
339(4)
6.1.9 Virtual Memory on the Intel 80386
343(5)
6.1.10 Virtual Memory on the Motorola 68030
348(4)
6.1.11 Comparison of the 80386 and 68030
352(1)
6.2 VIRTUAL I/O INSTRUCTIONS
353(10)
6.2.1 Sequential Files
354(2)
6.2.2 Random Access Files
356(1)
6.2.3 Implementation of Virtual I/O Instructions
357(4)
6.2.4 Directory Management Instructions
361(2)
6.3 VIRTUAL INSTRUCTIONS USED IN PARALLEL PROCESSING
363(9)
6.3.1 Process Creation
363(1)
6.3.2 Race Conditions
364(4)
6.3.3 Process Synchronization Using Semaphores
368(4)
6.4 EXAMPLE OPERATING SYSTEMS
372(18)
6.4.1 Examples of Virtual Memory
374(2)
6.4.2 Examples of Virtual I/O
376(11)
6.4.3 Examples of Process Management
387(2)
6.4.4 Comparison of UNIX and OS/2
389(1)
6.5 SUMMARY
390(7)
7 THE ASSEMBLY LANGUAGE LEVEL
397(34)
7.1 INTRODUCTION TO ASSEMBLY LANGUAGE
398(6)
7.1.1 What Is an Assembly Language?
398(1)
7.1.2 Format of an Assembly Language Statement
399(2)
7.1.3 Comparison of Assembly Language and High-Level Languages
401(1)
7.1.4 Program Tuning
402(2)
7.2 THE ASSEMBLY PROCESS
404(8)
7.2.1 Two-Pass Assemblers
404(1)
7.2.2 Pass One
405(3)
7.2.3 Pass Two
408(3)
7.2.4 Symbol Table
411(1)
7.3 MACROS
412(5)
7.3.1 Macro Definition, Call, and Expansion
412(3)
7.3.2 Macros with Parameters
415(1)
7.3.3 Implementation of a Macro Facility in an Assembler
416(1)
7.4 LINKING AND LOADING
417(10)
7.4.1 Tasks Performed by the Linker
418(3)
7.4.2 Structure of an Object Module
421(1)
7.4.3 Binding Time and Dynamic Relocation
422(3)
7.4.4 Dynamic Linking
425(2)
7.5 SUMMARY
427(4)
8 ADVANCED COMPUTER ARCHITECTURES
431(104)
8.1 RISC MACHINES
431(56)
8.1.1 Evolution of Computer Architecture
432(4)
8.1.2 Design Principles for RISC Machines
436(7)
8.1.3 Register Usage
443(7)
8.1.4 The Great RISC versus CISC Debate
450(7)
8.1.5 An Example RISC Architecture: SPARC
457(15)
8.1.6 A Second RISC Example: MIPS
472(15)
8.2 PARALLEL ARCHITECTURES
487(43)
8.2.1 Overview of Parallel Computers
488(6)
8.2.2 Disjoint-Memory MIMD Computers
494(4)
8.2.3 Bus-Based Shared-Memory Multiprocessors
498(7)
8.2.4 Multistage MIMD Shared-Memory Multiprocessors
505(7)
8.2.5 SIMD Parallel Computers and the Connection Machine
512(8)
8.2.6 SIMD Vector Computers
520(4)
8.2.7 Data Flow Computers
524(6)
8.3 SUMMARY
530(5)
9 READING LIST AND BIBLIOGRAPHY
535(18)
9.1 SUGGESTIONS FOR FURTHER READING
535(8)
9.1.1 Introduction and General Works
535(1)
9.1.2 Computer Systems Organization
536(1)
9.1.3 The Digital Logic Level
537(1)
9.1.4 The Microprogramming Level
537(1)
9.1.5 The Conventional Machine Level
538(1)
9.1.6 The Operating System Machine Level
538(1)
9.1.7 The Assembly Language Level
539(1)
9.1.8 Advanced Architectures
540(2)
9.1.9 Binary and Floating-Point Numbers
542(1)
9.2 ALPHABETICAL BIBLIOGRAPHY
543(10)
APPENDICES
553(22)
A BINARY NUMBERS
553(12)
A.1 FINITE-PRECISION NUMBERS
553(2)
A.2 RADIX NUMBER SYSTEMS
555(2)
A.3 CONVERSION FROM ONE RADIX TO ANOTHER
557(2)
A.4 NEGATIVE BINARY NUMBERS
559(3)
A.5 BINARY ARITHMETIC
562(3)
B FLOATING-POINT NUMBERS
565(10)
B.1 PRINCIPLES OF FLOATING POINT
566(3)
B.2 IEEE FLOATING-POINT STANDARD-754
569(6)
INDEX575
Andrew S. Tanenbaum is a professor of computer science at the Vrije Universiteit in Amsterdam where he has taught courses in computer organization, operating systems and networks for over 30 years to thousands of students

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