Rent 9780201533767 | Principles of CMOS VLSI Design : A Systems Perspective

Summary Table of Contents

With this revision, Weste conveys an understanding of CMOS technology, circuit design, layout, and system design sufficient to the designer. The book deals with the technology down to the layout level of detail, thereby providing a bridge from a circuit to a form that may be fabricated. The early chapters provide a circuit view of the CMOS IC design, the middle chapters cover a sub-system view of CMOS VLSI, and the final section illustrates these techniques using a real-world case study.

PART 1 INTRODUCTION TO CMOS TECHNOLOGY

(378)

Introduction to CMOS Circuits

(38)

A Brief History

(1)

... MORE

Book Summary

(1)

MOS Transistors

(2)

MOS Transistor Switches

(2)

CMOS Logic

(12)

The Inverter

(1)

Combinational Logic

(1)

The NAND Gate

(2)

The NOR Gate

(2)

Compound Gates

(2)

Multiplexers

(2)

Memory---Latches and Registers

(2)

Circuit and System Representations

(9)

Behavioral Representation

(2)

Structural Representation

(4)

Physical Representation

(2)

An Example

(8)

Specification

(1)

Behavioral Description

(1)

Structural Specification

(3)

Physical Description

(2)

Summary

(1)

CMOS Scorecard

(1)

Summary

(1)

References

(2)

MOS Transistor Theory

(68)

Introduction

(10)

nMOS Enhancement Transistor

(4)

pMOS Enhancement Transistor

(1)

Threshold Voltage

(1)

Threshold Voltage Equations

(3)

Body Effect

(1)

MOS Device Design Equations

(10)

Basic DC Equations

(2)

Second Order Effects

(1)

Threshold Voltage---Body Effect

(1)

Subthreshold Region

(1)

Channel-length Modulation

(1)

Mobility Variation

(1)

Fowler-Nordheim Tunneling

(1)

Drain Punchthrough

(1)

Impact Ionization---Hot Electrons

(1)

MOS Models

(1)

Small Signal AC Characteristics

(2)

The Complementary CMOS Inverter---DC Characteristics

(11)

βn/βp Ratio

(1)

Noise Margin

(2)

The CMOS Inverter as an Amplifier

(1)

Static Load MOS Inverters

(9)

The Pseudo-nMOS Inverter

(4)

Saturated Load Inverters

(1)

More Saturated Load Inverters

(2)

The Cascode Inverter

(1)

TTL Interface Inverter

(1)

The Differential Inverter

(5)

The Transmission Gate

(5)

The Tristate Inverter

(1)

Bipolar Devices

(7)

Diodes

(2)

Bipolar Transistors

(3)

BiCMOS Inverters

(2)

Summary

(1)

Exercises

(1)

Appendix---SPICE Level 3 Model

(7)

References

106

(3)

CMOS Processing Technology

109

(66)

Silicon Semiconductor Technology: An Overview

109

(8)

Wafer Processing

110

(1)

Oxidation

111

(1)

Expitaxy, Deposition, Ion-Implantation, and Diffusion

111

(2)

The Silicon Gate Process

113

(4)

Basic CMOS Technology

117

(13)

A basic n-well CMOS Process

117

(6)

The p-well Process

123

(1)

Twin-Tub Processes

124

(1)

Silicon On Insulator

125

(5)

CMOS Process Enhancements

130

(12)

Interconnect

130

(1)

Metal Interconnect

130

(2)

Polysilicon/Refractory Metal Interconnect

132

(1)

Local Interconnect

133

(1)

Circuit Elements

134

(1)

Resistors

134

(1)

Capacitors

134

(2)

Electrically Alterable ROM

136

(1)

Bipolar Transistors

136

(3)

Thin-film Transistors

139

(1)

3-D CMOS

140

(1)

Summary

141

(1)

Layout Design Rules

142

(14)

Layer Representations

143

(1)

CMOS n-well Rules

144

(6)

Design Rule Backgrounder

150

(5)

Scribe Line

155

(1)

Layer Assignments

155

(1)

SOI Rules

156

(1)

Design Rules---Summary

156

(1)

Latchup

156

(7)

The Physical Origin of Latchup

156

(2)

Latchup Triggering

158

(2)

Latchup Prevention

160

(1)

Internal Latchup Prevention Techniques

161

(1)

I/O Latchup Prevention

162

(1)

Technology-related CAD Issues

163

(4)

DRC---Spacing and Dimension Checks

164

(2)

Circuit Extraction

166

(1)

Summary

167

(1)

Exercises

167

(1)

Appendix---An n-well CMOS Technology Process Flow

168

(4)

References

172

(3)

Circuit Characterization and Performance Estimation

175

(86)

Introduction

175

(1)

Resistance Estimation

176

(4)

Resistance of Nonrectangular Regions

178

(1)

Contact and Via Resistance

179

(1)

Capacitance Estimation

180

(25)

MOS-Capacitor Characteristics

180

(3)

MOS Device Capacitances

183

(3)

Diffusion (source/drain) Capacitance

186

(2)

SPICE Modeling of MOS Capacitances

188

(3)

Routing Capacitance

191

(1)

Single Wire Capacitance

191

(1)

Multiple Conductor Capacitances

192

(6)

Distributed RC Effects

198

(4)

Capacitance Design Guide

202

(2)

Wire Length Design Guide

204

(1)

Inductance

205

(2)

Switching Characteristics

207

(19)

Analytic Delay Models

208

(1)

Fall Time

208

(2)

Rise Time

210

(1)

Delay Time

211

(2)

Empirical Delay Models

213

(1)

Gate Delays

214

(2)

Further Delay Topics

216

(1)

Input Waveform Slope

216

(1)

Input Capacitance

217

(1)

Switch-Level RC Models

218

(3)

Macromodeling

221

(2)

Body Effect

223

(2)

Summary

225

(1)

CMOS-Gate Transistor Sizing

226

(5)

Cascaded Complimentary Inverters

226

(2)

Cascaded Pseudo-nMOS Inverters

228

(1)

Stage Ratio

229

(2)

Power Dissipation

231

(7)

Static Dissipation

231

(2)

Dynamic Dissipation

233

(2)

Short-Circuit Dissipation

235

(1)

Total Power Dissipation

236

(1)

Power Economy

237

(1)

Sizing Routing Conductors

238

(2)

Power and Ground Bounce

239

(1)

Contact Replication

240

(1)

Charge Sharing

240

(3)

Design Margining

243

(5)

Temperature

243

(1)

Supply Voltage

244

(1)

Process Variation

245

(1)

Design Corners

246

(1)

Packaging Issues

247

(1)

Power and Clock Conductor Sizing

248

(1)

Summary

248

(1)

Yield

248

(2)

Reliability

250

(1)

Scaling of MOS Transistor Dimensions

250

(5)

Scaling Principles

251

(2)

Interconnect-Layer Scaling

253

(2)

Scaling in Practice

255

(1)

Summary

255

(1)

Exercises

256

(1)

References

257

(4)

CMOS Circuit and Logic Design

261

(118)

Introduction

261

(1)

CMOS Logic Gate Design

262

(11)

Fan-in and Fan-out

264

(3)

Typical CMOS NAND and NOR Delays

267

(4)

Transistor Sizing

271

(1)

Summary

272

(1)

Basic Physical Design of Simple Logic Gates

273

(22)

The Inverter

273

(5)

NAND and NOR gates

278

(1)

Complex Logic Gates Layout

279

(4)

CMOS Standard Cell Design

283

(2)

Gate Array Layout

285

(1)

Sea-of-Gates Layout

286

(1)

General CMOS Logic-Gate Layout Guidelines

287

(3)

Layout Optimization for Performance

290

(1)

Transmission-gate Layout Considerations

291

(3)

2-input Multiplexer

294

(1)

CMOS Logic Structures

295

(22)

CMOS Complementary Logic

295

(2)

BiCMOS Logic

297

(1)

Pseudo-nMOS Logic

298

(3)

Dynamic CMOS Logic

301

(1)

Clocked CMOS Logic (C2MOS)

302

(2)

Pass-transistor Logic

304

(4)

CMOS Domino Logic

308

(2)

NP Domino Logic (Zipper CMOS)

310

(1)

Cascade Voltage Switch Logic (CVSL)

311

(3)

SFPL Logic

314

(1)

Summary

315

(2)

Clocking Strategies

317

(40)

Clocked Systems

317

(1)

Latches and Registers

318

(4)

System Timing

322

(1)

Setup and Hold Time

323

(2)

Single-phase Memory Structures

325

(9)

Phase Locked Loop Clock Techniques

334

(3)

Metastability and Synchronization Failures

337

(3)

Single-phase Logic Structures

340

(4)

Two-phase Clocking

344

(2)

Two-phase Memory Structures

346

(4)

Two-phase Logic Structures

350

(1)

Four-phase Clocking

351

(1)

Four-phase Memory Structures

352

(1)

Four-phase Logic Structures

353

(2)

Recommended Clocking Approaches

355

(1)

Clock Distribution

356

(1)

I/O Structures

357

(11)

Overall Organization

357

(3)

VDD and VSS Pads

360

(1)

Output Pads

360

(1)

Input Pads

361

(3)

Tristate and Bidirectional Pads

364

(1)

Miscellaneous Pads

365

(2)

ECL and Low Voltage Swing Pads

367

(1)

Low-power Design

368

(2)

Summary

370

(1)

Exercises

370

(2)

References

372

(7)

PART 2 SYSTEMS DESIGN AND DESIGN METHODS

379

(246)

CMOS Design Methods

381

(84)

Introduction

381

(1)

Design Strategies

382

(9)

Introduction

382

(1)

Structured Design Strategies

383

(1)

Hierarchy

384

(3)

Regularity

387

(1)

Modularity

387

(2)

Locality

389

(2)

Summary

391

(1)

CMOS Chip Design Options

391

(33)

Programmable Logic

391

(1)

Programmable Logic Structures

392

(3)

Programmable Interconnect

395

(5)

Reprogrammable Gate Arrays

400

(1)

The XILINX Programmable Gate Array

400

(3)

Algotronix

403

(3)

Concurrent Logic

406

(1)

Sea-of-Gate and Gate Array Design

407

(6)

Standard-cell Design

413

(1)

A Typical Standard-cell Library

414

(3)

Full-custom Mask Design

417

(1)

Symbolic Layout

417

(1)

Coarse-grid Symbolic Layout

417

(1)

Gate-matrix Layout

418

(2)

Sticks Layout and Compaction

420

(1)

Virtual-grid Symbolic Layout

421

(2)

Process Migration---Retargetting Designs

423

(1)

Design Methods

424

(13)

Behavioral Synthesis

424

(1)

RTL Synthesis

425

(2)

Logic Optimization

427

(4)

Structural-to-Layout Synthesis

431

(1)

Placement

431

(1)

Routing

431

(1)

An Automatic Placement Example

432

(2)

Layout Synthesis

434

(3)

Design-capture Tools

437

(3)

HDL Design

437

(1)

Schematic Design

438

(1)

Layout Design

438

(1)

Floorplanning

438

(1)

Chip Composition

439

(1)

Design Verification Tools

440

(9)

Simulation

441

(1)

Circuit-level Simulation

441

(1)

Timing Simulation

442

(1)

Logic-level Simulation

443

(1)

Switch-level Simulation

444

(1)

Mixed-mode Simulators

444

(1)

Summary

445

(1)

Timing Verifiers

445

(1)

Network Isomorphism

446

(1)

Netlist comparison

447

(1)

Layout Extraction

448

(1)

Back-Annotation

448

(1)

Design-rule Verification

448

(1)

Pattern Generation

448

(1)

Design Economics

449

(7)

Nonrecurring Engineering Costs (NREs)

450

(1)

Engineering Costs

450

(1)

Prototype Manufacturing Costs

451

(1)

Recurring Costs

452

(1)

Fixed Costs

452

(1)

Schedule

453

(1)

Personpower

454

(1)

An Example---Gate-array Productivity

454

(2)

Data Sheets

456

(2)

The Summary

456

(1)

Pinout

456

(1)

Description of Operation

457

(1)

DC Specifications

457

(1)

AC Specifications

457

(1)

Package Diagram

458

(1)

Summary

458

(1)

Exercises

458

(1)

References

459

(6)

CMOS Testing

465

(48)

The Need for Testing

465

(6)

Functionality Tests

466

(2)

Manufacturing Tests

468

A Walk Through the Test Process

456

(15)

Manufacturing Test Principles

471

(14)

Fault models

472

(1)

Stuck-At Faults

472

(1)

Short-Circuit and Open-Circuit Faults

473

(1)

Observability

474

(1)

Controllability

475

(1)

Fault Coverage

475

(1)

Automatic Test Pattern Generation (ATPG)

476

(5)

Fault Grading and Fault Simulation

481

(1)

Delay Fault Testing

482

(1)

Statistical Fault Analysis

483

(1)

Fault Sampling

484

(1)

Design Strategies for Test

485

(13)

Design for Testability

485

(1)

Ad-Hoc Testing

485

(4)

Scan-Based Test Techniques

489

(1)

Level Sensitive Scan Design (LSSD)

489

(1)

Serial Scan

490

(3)

Partial Serial Scan

493

(1)

Parallel Scan

493

(2)

Self-Test Techniques

495

(1)

Signature Analysis and BILBO

495

(2)

Memory Self-Test

497

(1)

Iterative Logic Array Testing

498

(1)

IDDQ Testing

498

(1)

Chip-Level Test Techniques

498

(2)

Regular Logic Arrays

499

(1)

Memories

500

(1)

Random logic

500

(1)

System-Level Test Techniques

500

(6)

Boundary Scan

500

(1)

Introduction

500

(1)

The Test Access Port (TAP)

501

(1)

The Test Architecture

502

(1)

The Tap Controller

502

(1)

The Instruction Register (IR)

503

(1)

Test-Data Registers (DRs)

504

(1)

Boundary Scan Registers

504

(2)

Summary

506

(1)

Layout Design for Improved Testability

506

(2)

Summary

508

(1)

Exercises

508

(1)

References

508

(5)

CMOS Subsystem Design

513

(112)

Introduction

513

(1)

Datpath Operations

513

(50)

Addition/Subtraction

515

(1)

Single-Bit Adders

515

(2)

Bit-Parallel Adder

517

(3)

Bit Serial Adders, Carry-save Addition, and Pipelining

520

(4)

Transmission-Gate Adder

524

(2)

Carry-Lookahead Adders

526

(6)

Carry-Select Adder

532

(1)

Conditional-Sum Adder

532

(2)

Very Wide Adders

534

(2)

Summary

536

(1)

Parity Generators

537

(1)

Comparators

537

(1)

Zero/One Detectors

537

(2)

Binary Counters

539

(1)

Asynchronous Counters

539

(1)

Synchronous Counters

539

(2)

Boolean Operations---ALUs

541

(1)

Multiplication

542

(3)

Array Multiplication

545

(2)

Radix-n Multiplication

547

(7)

Wallace Tree Multiplication

554

(3)

Serial Multiplication

557

(3)

Shifters

560

(3)

Memory Elements

563

(27)

Read/Write Memory

564

(1)

RAM

564

(16)

580

(2)

FIFOs, LIFOs, SIPOs

582

(1)

Serial-Access Memory

583

(2)

Read Only Memory

585

(4)

Content-Addressable Memory

589

(1)

Control

590

(30)

Finite-State Machines

591

(1)

FSM Design Procedure

591

(4)

Control Logic Implementation

595

(1)

PLA Control Implementation

595

(7)

ROM Control Implementation

602

(2)

Multilevel Logic

604

(1)

An Example of Control-Logic Implementation

604

(16)

Summary

620

(1)

Exercises

621

(1)

References

622

(3)

PART 3 CMOS SYSTEM CASE STUDIES

625

(78)

CMOS System Design Examples

627

(76)

Introduction

627

(1)

A Core RISC Microcontroller

628

(44)

Instruction Set

629

(1)

Address Architecture

629

(2)

ALU Class Instructions

631

(2)

Control Transfer Instructions

633

(1)

Pipeline Architecture

634

(3)

Bypassing, Result Forwarding, or Pass-around

637

(1)

Conditional Branching

638

(1)

Subroutine Call and Return

639

(1)

I/O Architecture

639

(1)

Major Logic Blocks

640

(1)

ALU_DP

640

(11)

651

(3)

PC Datapath (PC_DP)

654

(2)

Instruction Memory

656

(1)

Instruction Pipe

656

(2)

Control Logic

658

(5)

Layout

663

(3)

Datapath Floorplans

666

(3)

Functional Verification and Testing

669

(3)

A TV Echo Canceller

672

(22)

Ghost Cancellation

672

(2)

FIR and IIR filters

674

(2)

System Architecture

676

(1)

Chip Architecture

677

(1)

Filter Considerations

677

(1)

Chip Overview

678

(2)

Submodules

680

(1)

Filter Taps

680

(5)

Delay Lines

685

(1)

Phase-locked Loop- and Clock-generation

685

(4)

Peripheral Processing

689

(1)

Power Distribution

689

(1)

Chip Floorplan

690

(2)

Testing and Verification

692

(2)

Summary

694

(1)

A 6-bit Flash A/D

694

(7)

Introduction

694

(1)

Basic Architecture

695

(1)

Resistor String

696

(1)

The Comparator

696

(2)

Thermometer Code Logic

698

(1)

Floorplan and Layout

698

(3)

Summary

701

(1)

Summary

701

(1)

Exercises

701

(1)

References

702

(1)

Index

703

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