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High-Speed Signaling Jitter Modeling, Analysis, and Budgeting

ISBN: 9780132826914 | 0132826917
Edition: 1st
Format: Hardcover
Publisher: Prentice Hall
Pub. Date: 10/6/2011

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As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial, and high-speed signal integrity engineering has grown into one of today's most important engineering disciplines. This book brings together cutting-edge contributions from the field's most respected practitioners and researchers, including leaders at Rambus, MIT, and the University of California, Berkeley. Edited by pioneering experts Dan Oh and Chuck Yuan, these contributors illuminate the newest design challenges in signal integrity and power integrity (SI/PI). They summarize emerging issues and new modeling/analysis methodologies used by leading companies such as Rambus, Intel, and IBM; and thoroughly cover high-speed signaling analysis, including signal and power integrity with on-chip device jitter. Throughout, this book focuses on understanding the "big picture" - now essential to predicting overall link performance. You will find innovative modeling and design methodologies for high-speed signaling, including statistical link simulation; experiment design; signal conditioning (EQ); modeling on-chip noise; modeling random and power-supply noise; on-chip measurement, and more. Published and validated in numerous conferences and journals, all these techniques are now described in detail in easy-to-read book format for the first time.


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